Advanced Transfer Cache - определение. Что такое Advanced Transfer Cache
Diclib.com
Словарь ChatGPT
Поиск в словаре Индивидуальные решения
Введите слово или словосочетание на любом языке 👆
Язык:

Перевод и анализ слов искусственным интеллектом ChatGPT

На этой странице Вы можете получить подробный анализ слова или словосочетания, произведенный с помощью лучшей на сегодняшний день технологии искусственного интеллекта:

  • как употребляется слово
  • частота употребления
  • используется оно чаще в устной или письменной речи
  • варианты перевода слова
  • примеры употребления (несколько фраз с переводом)
  • этимология
  1. Словари
  2. Английский словарь
  3. Advanced Transfer Cache

Что (кто) такое Advanced Transfer Cache - определение

LINE OF DESKTOP AND MOBILE MICROPROCESSORS PRODUCED BY INTEL
Pentium 3; Pentium iii; Coppermine (microprocessor); Pentium !!!; Pentium III class; Advanced Transfer Cache; Intel pentium iii; Intel Pentium III Processor; P!!!; Intel Pentium 3; Intel Pentium III; PIII; P III; Processor Serial Number; Personal Serial Number; Pentium Three; Mobile Pentium III; Pentium III M; Katmai (microprocessor); Tualatin (microprocessor); Coppermine T (microprocessor)
  • Tualatin die shot
  • Coppermine Die shot
  • Katmai Die shot
  • Pentium III-M Logo (1999-2003)
  • A Pentium III ''Katmai'' SECC2 cartridge with heatsink removed.
  • Pentium III logo (1999-2003)
  • A 900 MHz ''Coppermine'' FC-PGA Pentium III.
  • A 1.13 GHz FC-PGA2 ''Tualatin-256'' Intel Pentium III-T.
  • Slot 1 Pentium III CPU mounted on a motherboard
Найдено результатов: 1958
secondary cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
<memory management> (Or "second level cache", "level two cache", "L2 cache") A larger, slower cache between the primary cache and main memory. Whereas the primary cache is often on the same integrated circuit as the {central processing unit} (CPU), a secondary cache is usually external. (1997-06-25)
Web cache         
MECHANISM FOR THE TEMPORARY STORAGE (CACHING) OF WEB DOCUMENTS
Web caching; HTTP cache; Browser Cache; Browser Caching; Squirrel (DHT); Squirrel dht; Web caches; Proxy cache; Browser cache; Cache server; Internet cache; Http cache; HTTP caching; Webcache; Cache-Control; Web browser cache; Bypass your cache; Webcaching; List of server-side web caching software; Forward cache; Reverse cache
A Web cache (or HTTP cache) is a system for optimizing the World Wide Web. It is implemented both client-side and server-side.
https://en.wikipedia.org/wiki/Web_cache
cache line         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
<storage> (Or cache block) The smallest unit of memory than can be transferred between the main memory and the cache. Rather than reading a single word or byte from main memory at a time, each cache entry is usually holds a certain number of words, known as a "cache line" or "cache block" and a whole line is read and cached at once. This takes advantage of the principle of locality of reference: if one location is read then nearby locations (particularly following locations) are likely to be read soon afterward. It can also take advantage of page-mode DRAM which allows faster access to consecutive locations. (1997-01-21)
level 1 cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
primary cache
L2 cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
secondary cache
cache block         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
cache line
L1 cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
primary cache
level 2 cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
secondary cache
CPU cache         
  • Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
  • Memory hierarchy of an AMD Bulldozer server
  • Austek]] A38202; to the right of the processor)
  • [[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations.
https://en.wikipedia.org/wiki/CPU_cache
Cache hierarchy         
  • alt=a memory system diagram showing a copy of the L1 within L2 and a copy of the L2 within L3.
  • url-status=dead}}</ref>
  • alt=three squares showing separated on-CPU L1 caches for instructions and data, an off-chip L2 cache, and main memory.
  • alt=Three CPUs each have private on-chip L1 caches but share the off-chip L2, L3, and main memory.
MEMORY HIERARCHY CONCEPT APPLIED TO CPU CACHES WITH MULTIPLE LEVELS
Cache Hierarchy
Cache hierarchy, or multi-level caches, refers to a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly requested data is cached in high-speed access memory stores, allowing swifter access by central processing unit (CPU) cores.
https://en.wikipedia.org/wiki/Cache_hierarchy

Википедия

Pentium III

The Pentium III (marketed as Intel Pentium III Processor, informally PIII or P3) brand refers to Intel's 32-bit x86 desktop and mobile CPUs based on the sixth-generation P6 microarchitecture introduced on February 28, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded processors. The most notable differences were the addition of the Streaming SIMD Extensions (SSE) instruction set (to accelerate floating point and parallel calculations), and the introduction of a controversial serial number embedded in the chip during manufacturing. The Pentium III is also a single-core processor.

Even after the release of the Pentium 4 in late 2000, the Pentium III continued to be produced with new models introduced until early 2003, and were discontinued in April 2004 for desktop units, and May 2007 for mobile units.

https://en.wikipedia.org/wiki/Pentium III
Поиск в словаре
Все словари Английский словарь Англо-арабский словарь Англо-голландский словарь Англо-греческий словарь Англо-испанский словарь Англо-итальянский словарь Англо-немецкий словарь Англо-русский словарь Англо-французский словарь Арабский словарь Голландский словарь Греческий словарь Испанский словарь Итальянский словарь Итальянско-русский словарь Латинско-испанский словарь Латинско-португальский словарь Немецкий словарь Португальский словарь Португальско-русский словарь Русский словарь Французский словарь Французско-русский словарь
Создано ИИ
Английский Русский Испанский Португальский Немецкий Французский Греческий Голландский Итальянский Арабский
Язык интерфейса
Русский English Español Português Deutsch Français Ελληνικά Nederlands Italiano عربي
Контакты
Свяжитесь с нами



Конфиденциальность
Политика конфиденциальности